Integrated circuits that include MOS transistors are particularly susceptible to damage by electrostatic discharge (ESD) events, e.g. when the circuit is touched by a person handling the circuit causing static electricity to discharge from the handler through the circuit. This is particularly the case once the circuit has been packaged but prior to it being installed in a product.
In the case of an EEPROM device, ESD events or other electrical overstress events can cause the device to be reprogrammed. Even though the programming of an EEPROM requires a certain voltage combination on the erase and enable pins of the EEPROM, the high voltages provided by an ESD event together with the effect of coupling with other pins can cause a reprogramming of the EEPROM.
A prior art solution to this problem is shown schematically in FIG. 1, which shows an SCR 100 connected to the erase pins of a memory array, as depicted by the memory array capacitance 102. The schematic representation depicts the electrical connections as having a resistance 104 and capacitance 106.
Test results have however shown that due to the low leakage associated with these memory devices, ESD events as well as low current overstress events cause long term storage of residual voltage in the memory devices. Even the use of snapback ESD protection devices therefore does not always provide a satisfactory solution. In fact an overstress event followed by an ESD event may cause particularly high residual voltage if the electrical overstress event is below the triggering voltage of the snapback device.
Furthermore, the erase voltage used during normal operation of the memory device is itself a high voltage, of the order of 20V, and thus threatens to trigger the snapback device during normal operation.
The present invention seeks to provide a solution to these problems